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Computer Architecture. Instructor: Prof. Anshul Kumar, Department of Computer Science and Engineering, IIT Delhi.
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Description
The aim of this course is to learn how computers work, the basic principles common across all computers, how to analyze their performance, how computers are designed and built, and issues affecting modern processors such as caches and pipelines. Topics covered in the lectures include: history of computers, instruction set architecture, performance evaluation of processors, ALU design, multiplier design, divider design, floating point arithmetic, processor design, pipelined processor design, memory hierarchy, and input/output subsystem. (from nptel.ac.in)
Course content
- Lecture 01 – Introduction to Computer Architecture Unlimited
- Lecture 02 – History of Computers Unlimited
- Lecture 03 – Instruction Set Architecture I Unlimited
- Lecture 04 – Instruction Set Architecture II Unlimited
- Lecture 05 – Instruction Set Architecture III Unlimited
- Lecture 06 – Recursive Programs Unlimited
- Lecture 07 – Architecture Space: Features of MIPS ISA, RISC and CISC Unlimited
- Lecture 08 – Architecture Examples: PowerPC, SPARC, VAX, Intel x86 Unlimited
- Lecture 09 – Performance and Cost Unlimited
- Lecture 10 – Performance Evaluation of Processors Unlimited
- Lecture 11 – Binary Arithmetic, ALU Design Unlimited
- Lecture 12 – ALU Design, Overflow Unlimited
- Lecture 13 – Multiplier Design Unlimited
- Lecture 14 – Divider Design Unlimited
- Lecture 15 – Fast Addition, Multiplication Unlimited
- Lecture 16 – Floating Point Arithmetic Unlimited
- Lecture 17 – Processor Design: Introduction Unlimited
- Lecture 18 – Processor Design: Simple Design Unlimited
- Lecture 19 – Processor Design: Simple Design (cont.) Unlimited
- Lecture 20 – Processor Design: Multi Cycle Approach Unlimited
- Lecture 21 – Processor Design: Control for Multi Cycle Unlimited
- Lecture 22 – Processor Design: Microprogrammed Control Unlimited
- Lecture 23 – Processor Design: Exception Handling Unlimited
- Lecture 24 – Pipelined Processor Design: Basic Idea Unlimited
- Lecture 25 – Pipelined Processor Design: Data Path and Control Unlimited
- Lecture 26 – Pipelined Processor Design: Handling Data Hazards Unlimited
- Lecture 27 – Pipelined Processor Design: Handling Control Hazards Unlimited
- Lecture 28 – Memory Hierarchy: Basic Idea Unlimited
- Lecture 29 – Memory Hierarchy: Cache Organization Unlimited
- Lecture 30 – Memory Hierarchy: Cache Organization (cont.) Unlimited
- Lecture 31 – Memory Hierarchy: Virtual Memory Unlimited
- Lecture 32 – Memory Hierarchy: Virtual Memory (cont.) Unlimited
- Lecture 33 – Input/Output Subsystem: Introduction Unlimited
- Lecture 34 – Input/Output Subsystem: Interfaces and Buses Unlimited
- Lecture 35 – Input/Output Subsystem: Interfaces and Buses (cont.) Unlimited
- Lecture 36 – Input/Output Subsystem: I/O Operations Unlimited
- Lecture 37 – Input/Output Subsystem: Designing I/O Systems Unlimited
- Lecture 38 – Concluding Remarks Unlimited
Instructor
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