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6.004 offers an introduction to the engineering of digital systems. Starting with MOS transistors, the course develops a series of building blocks — logic gates, combinational and sequential circuits, finite-state machines, computers and finally complete systems.

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English

English [CC]

FREE

Description

Both hardware and software mechanisms are explored through a series of design examples.

6.004 is required material for any EECS undergraduate who wants to understand (and ultimately design) digital systems. A good grasp of the material is essential for later courses in digital design, computer architecture and systems. The problem sets and lab exercises are intended to give students “hands-on” experience in designing digital systems; each student completes a gate-level design for a reduced instruction set computer (RISC) processor during the semester.

Course content

  • Course overview and mechanics, basics of information Unlimited
  • Digital abstraction, combinational logic, voltage-based encoding Unlimited
  • CMOS technology, gate design, timing Unlimited
  • Canonical forms; synthesis, simplification Unlimited
  • Sequential logic Unlimited
  • Storage elements, finite state machines Unlimited
  • Synchronization, metastability Unlimited
  • Pipelining; throughput and latency Unlimited
  • Case study: multipliers Unlimited
  • Beta instruction set architecture, compilation Unlimited
  • Machine language programming issues Unlimited
  • Models of computation, programmable architectures Unlimited
  • Stacks and procedures Unlimited
  • Non-pipelined Beta implementation Unlimited
  • Multilevel memories; locality, performance, caches Unlimited
  • Cache design issues Unlimited
  • Virtual memory: mapping, protection, contexts Unlimited
  • Virtual machines: timesharing, OS kernels, supervisor calls Unlimited
  • Devices and interrupt handlers, preemptive interrupts, real-time issues Unlimited
  • Communication issues: busses, networks, protocols Unlimited
  • Communicating processes: semaphores, synchronization, atomicity, deadlock Unlimited
  • Pipelined Beta implementation, bypassing Unlimited
  • Pipeline issues: delay slots, annulment, exceptions Unlimited
  • Parallel processing, shared memory, cache coherence, consistency criteria Unlimited
  • Wrapup lecture Unlimited

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Instructor

Massachusetts Institute of Technology
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