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Advanced VLSI Design. Instructors: Prof. A. N. Chandorkar, Prof. D. K. Sharma, Prof. Sachin Patkar, and Prof. Virendra K. Singh, Department of Electrical Engineering, IIT Bombay.

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September 25, 2023

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September 25, 2023

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FREE

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Description

Advanced VLSI Design. Instructors: Prof. A. N. Chandorkar, Prof. D. K. Sharma, Prof. Sachin Patkar, and Prof. Virendra K. Singh, Department of Electrical Engineering, IIT Bombay.

This course covers topics in VLSI design: Historical perspective of VLSI, CMOS VLSI design for power and speed consideration, Logical effort, Designing fast CMOS circuits, Datapath design, Interconnect aware design, Hardware description Languages for VLSI design, FSM controller/datapath and processor design, VLSI design automation, and VLSI design test and verification. (from nptel.ac.in)

Course Curriculum

  • Lecture 01 – Historical Perspective and Future Trends in CMOS VLSI Circuit and System Design Unlimited
  • Lecture 02 – Historical Perspective and Future Trends in CMOS VLSI Circuit and System Design Unlimited
  • Lecture 03 – Logical Effort – A Way of Designing Fast CMOS Circuits Unlimited
  • Lecture 04 – Logical Effort – A Way of Designing Fast CMOS Circuits (cont.) Unlimited
  • Lecture 05 – Logical Effort – A Way of Designing Fast CMOS Circuits (cont.) Unlimited
  • Lecture 06 – Power Estimation and Control in CMOS VLSI Circuits Unlimited
  • Lecture 07 – Power Estimation and Control in CMOS VLSI Circuits (cont.) Unlimited
  • Lecture 08 – Low Power Design Techniques Unlimited
  • Lecture 09 – Low Power Design Techniques (cont.) Unlimited
  • Lecture 10 – Arithmetic Implementation Strategies for VLSI Unlimited
  • Lecture 11 – Arithmetic Implementation Strategies for VLSI (cont.) Unlimited
  • Lecture 12 – Arithmetic Implementation Strategies for VLSI (cont.) Unlimited
  • Lecture 13 – Arithmetic Implementation Strategies for VLSI (cont.) Unlimited
  • Lecture 14 – Interconnect Aware Design: Impact of Scaling, Buffer Insertion and Inductive Peaking Unlimited
  • Lecture 15 – Interconnect Aware Design: Low Swing and Current Mode Signaling Unlimited
  • Lecture 16 – Interconnect Aware Design: Capacitively Coupled Interconnects Unlimited
  • Lecture 17 – Introduction to Hardware Description Languages Unlimited
  • Lecture 18 – Managing Concurrency and Time in Hardware Description Languages Unlimited
  • Lecture 19 – Introduction to VHDL Unlimited
  • Lecture 20 – Basic Components in VHDL Unlimited
  • Lecture 21 – Structural Description in VHDL Unlimited
  • Lecture 22 – Behavioral Description in VHDL Unlimited
  • Lecture 23 – Introduction to Verilog Unlimited
  • Lecture 24 – Finite State Machine + Datapath (GCD Example) Unlimited
  • Lecture 25 – FSM + Datapath (cont.) Unlimited
  • Lecture 26 – Single cycle MMIPS Unlimited
  • Lecture 27 – Multicycle MMIPS Unlimited
  • Lecture 28 – Multicycle MMIPS? FSM Unlimited
  • Lecture 29 – Brief Overview of Basic VLSI Design Automation Concepts Unlimited
  • Lecture 30 – Netlist and System Partitioning Unlimited
  • Lecture 31 – Timing Analysis in the Context of Physical Design Automation Unlimited
  • Lecture 32 – Placement Algorithm Unlimited
  • Lecture 33 – Introduction to VLSI Testing Unlimited
  • Lecture 34 – VLSI Test Basics Unlimited
  • Lecture 35 – VLSI Test Basics (cont.) Unlimited
  • Lecture 36 – VLSI Testing: Automatic Test Pattern Generation Unlimited
  • Lecture 37 – VLSI Testing: Design for Test Unlimited
  • Lecture 38 – VLSI Testing: Built-In-Self Test Unlimited
  • Lecture 39 – VLSI Design Verification: An Introduction Unlimited
  • Lecture 40 – VLSI Design Verification (cont.) Unlimited
  • Lecture 41 – VLSI Design Verification: Equivalence/Model Checking Unlimited
  • Lecture 42 – VLSI Design Verification: Model Checking Unlimited

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