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Computer Architecture. Instructor: Prof. Madhu Mutyam, Department of Computer Science and Engineering, IIT Madras.

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September 25, 2023

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Last updated:

September 25, 2023

Duration:

Unlimited Duration

FREE

This course includes:

Unlimited Duration

Badge on Completion

Certificate of completion

Unlimited Duration

Description

Computer Architecture. Instructor: Prof. Madhu Mutyam, Department of Computer Science and Engineering, IIT Madras.

Computer architecture course deals with instruction set architecture, microarchitecture and efficient implementation of microarchitecture. Understanding the computer architecture concepts is essential for students interested in hardware, processor design, compilers, and operating systems.

In the last four decades, the number of transistors in a chip has increased from few thousands to few billions. In order to utilize the available transistors in a chip to improve computational power, various micro-architectural techniques have been proposed, which lead to the design of variety of processors, from simple in-order pipeline processors to recent multi-core processors. The course provides a detailed understanding of various processor microarchitectural designs, which include in-order scalar pipeline design, out-of-order superscalar processor design, and multicore processor design. (from nptel.ac.in)

Course Curriculum

  • Lecture 01 – Introduction to Computer Architecture Unlimited
    • Lecture 02 – Quantitative Principles of Computer Design Unlimited
    • Lecture 03 – Instruction Set Principles: The Role of ISA, ISA Classification, Memory Addressing Unlimited
    • Lecture 04 – Instruction Set Principles: Addressing Modes Unlimited
    • Lecture 05 – Instruction Set Principles: Types of Operands and Operations, Encoding an ISA Unlimited
    • Lecture 06 – Cache Memory Hierarchy Unlimited
    • Lecture 07 – Cache Memory Hierarchy: The Basics of Cache Memory Unlimited
    • Lecture 08 – Cache Memory Hierarchy: Basic Cache Optimizations Unlimited
    • Lecture 09 – Cache Memory Hierarchy: Advanced Optimizations Unlimited
    • Lecture 10 – Main Memory Design: Basics of DRAM based Memory Unlimited
    • Lecture 11 – Main Memory Design: DRAM based Memory Controller Design Unlimited
    • Lecture 12 – Main Memory Design: DRAM based Memory Controller Design (cont.) Unlimited
    • Lecture 13 – Pipelining Concept and Examples Unlimited
    • Lecture 14 – Instruction Pipelining Unlimited
    • Lecture 15 – Pipeline Hazards Unlimited
    • Lecture 16 – Handling Pipeline Hazards Unlimited
    • Lecture 17 – Implementation of MIPS pipeline Unlimited
    • Lecture 18 – Scalar Pipeline to Superscalar Pipeline Unlimited
    • Lecture 19 – Instruction Dependencies Unlimited
    • Lecture 20 – Compiler Optimizations for Exposing ILP Unlimited
    • Lecture 21 – Advanced Branch Prediction Techniques: Correlated Branch Predictors Unlimited
    • Lecture 22 – Advanced Branch Prediction Techniques: Tournament Branch Predictor Unlimited
    • Lecture 23 – Superscalar Organization Unlimited
    • Lecture 24 – Register Renaming Unlimited
    • Lecture 25 – Tomasulo Algorithm Unlimited
    • Lecture 26 – Dynamic Execution Core Unlimited
    • Lecture 27 – Multithreading Unlimited
    • Lecture 28 – Multicore Processors Unlimited
    • Lecture 29 – Cache Coherence Unlimited
    • Lecture 30 – Cache Coherence Protocol Design Unlimited
    • Lecture 31 – Synchronization Unlimited
    • Lecture 32 – Memory Consistency: Sequential Consistency Model Unlimited
    • Lecture 33 – Memory Consistency: Total Store Order and Relaxed Consistency Models Unlimited

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