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Last updated:

September 25, 2023

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Description

Digital System Design. Instructor: Prof. Neeraj Goel, Department of Computer Science and Engineering, IIT Ropar

Digital system design course focuses on designing digital systems from scratch. The course focuses on designing combinational and sequential building blocks, using these building blocks to design bigger digital systems. During this course we also learn how to use Verilog to design/model a digital system. (from nptel.ac.in)

Course Curriculum

  • Lecture 01 – Introduction Unlimited
  • Lecture 02 – Analog vs Digital Unlimited
  • Lecture 03 – Binary Number System, Part 1 Unlimited
  • Lecture 04 – Binary Number System, Part 2 Unlimited
  • Lecture 05 – Negative Number Representation, Part 1 Unlimited
  • Lecture 06 – Negative Number Representation, Part 2 Unlimited
  • Lecture 07 – Other Number Systems Unlimited
  • Lecture 08 – Floating Point Numbers, Part 1 Unlimited
  • Lecture 09 – Floating Point Numbers, Part 2 Unlimited
  • Lecture 10 – Floating Point Numbers, Part 3 Unlimited
  • Lecture 11 – Floating Point Numbers, Part 4 Unlimited
  • Lecture 12 – Floating Point Numbers, Part 5 Unlimited
  • Lecture 13 – Boolean Functions Unlimited
  • Lecture 14 – Boolean Algebra Unlimited
  • Lecture 15 – SOP and POS Representation Unlimited
  • Lecture 16 – Algebraic Simplifications Unlimited
  • Lecture 17 – Canonical Form Unlimited
  • Lecture 18 – Boolean Minimization using Karnaugh Maps Unlimited
  • Lecture 19 – More Logic Gates Unlimited
  • Lecture 20 – Hardware Description Language: Verilog Unlimited
  • Lecture 21 – Verilog Simulation Demo Unlimited
  • Lecture 22 – Karnaugh Maps Unlimited
  • Lecture 23 – Quine-McCluskey Method Unlimited
  • Lecture 24 – Area Delay Model Unlimited
  • Lecture 25 – Multi-Level Logic Unlimited
  • Lecture 26 – Multiplexer Unlimited
  • Lecture 27 – Four Stage Logic Unlimited
  • Lecture 28 – Decoders, Part 1 Unlimited
  • Lecture 29 – Decoders, Part 2 Unlimited
  • Lecture 30 – Encoders Unlimited
  • Lecture 31 – Programmable Hardware Unlimited
  • Lecture 32 – Ripple Carry Adder Unlimited
  • Lecture 33 – Carry Look Ahead Adder Unlimited
  • Lecture 34 – Modeling BUS in Verilog Unlimited
  • Lecture 35 – Fast Adder: Carry Select Adder Unlimited
  • Lecture 36 – Multiple Operand Adder Unlimited
  • Lecture 37 – Multiplication Unlimited
  • Lecture 38 – Iterative Circuits, Part 1 Unlimited
  • Lecture 39 – Iterative Circuits, Part 2 Unlimited
  • Lecture 40 – Introduction to Sequential Circuits Unlimited
  • Lecture 41 – Latches Unlimited
  • Lecture 42 – D-Flip-Flops Unlimited
  • Lecture 43 – More Flip-Flops Unlimited
  • Lecture 44 – Counters Unlimited
  • Lecture 45 – Verilog Behavior Model, Part 1 Unlimited
  • Lecture 46 – Verilog Behavior Model, Part 2 Unlimited
  • Lecture 47 – Registers, Part 1 Unlimited
  • Lecture 48 – Registers, Part 2 Unlimited
  • Lecture 49 – Memory Unlimited
  • Lecture 50 – Sequential Circuit Analysis Unlimited
  • Lecture 51 – Derivation State Graph Unlimited
  • Lecture 52 – Sequence Detector: Example 1 Unlimited
  • Lecture 53 – Sequence Detector: Example 2 Unlimited
  • Lecture 54 – State Machine Reduction Unlimited
  • Lecture 55 – State Encoding Unlimited
  • Lecture 56 – Multicycle Adder Design Unlimited
  • Lecture 57 – Pipelined Adder Design Unlimited
  • Lecture 58 – Multiplication Design Unlimited
  • Lecture 59 – Division Hardware Design Unlimited
  • Lecture 60 – Interacting State Machines Unlimited
  • Lecture 61 – Register Transfer Level Design Unlimited
  • Lecture 62 – GCD Computer at RTL Level Unlimited
  • Lecture 63 – RTL Design: Bubble Sort Unlimited
  • Lecture 64 – RTL Design: Traffic Light Controller Unlimited
  • Lecture 65 – FPGA (Field Programmable Gate Array) Unlimited
  • Lecture 66 – Xilinx CLB Unlimited
  • Lecture 67 – FPGA Design Flow Unlimited
  • Lecture 68 – FPGA Design Demo Unlimited

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