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September 25, 2023


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How Computer Works (ArsDigita University). Taught by Gill Pratt,

this course provides an introduction to the basics of digital logic design, computer organization and architecture including assembly language, processor design, memory hierarchies and pipelining. Students examine the detailed construction of a very simple computer. Problem sets use Beta-Sim, a RISC simulator written by Mike Wessler. A higher level view of a modern RISC architecture is studied, using the Patterson and Hennessey introductory text, from both the programmer's point of view and the hardware designer's point of view. The distinction between RISC and CISC architectures is emphasized. (from ADUni.org)

Course Curriculum

  • Lecture 01 – Introduction to the BETA ISA Unlimited
  • Lecture 02 – Storage Allocation, Stack Discipline, Calling Conventions Unlimited
  • Lecture 03 – Unpipelined Beta, Exceptions Unlimited
  • Lecture 04 – Implementing the ALU Unlimited
  • Lecture 04b – Recitation 1 Unlimited
  • Lecture 05 – Implementation of Beta Memorie Unlimited
  • Lecture 05b – Recitation 2 Unlimited
  • Lecture 06 – Synchronous Finite State Machines (FSMs) Unlimited
  • Lecture 07 – Flip-flops, Asynchronous FSMs, Dynamic Discipline, Timing Unlimited
  • Lecture 08 – Arbitration and Metastability Unlimited
  • Lecture 09 – Static Discipline, Transistor-level design Unlimited
  • Lecture 10 – Physics of Communication and Computation Unlimited
  • Lecture 11 – Physics of Computation Unlimited
  • Lecture 12 – Pipelining Unlimited
  • Lecture 13 – Details of the Pipelined Beta Unlimited
  • Lecture 14 – Caches Unlimited
  • Lecture 15 – Virtual Memory, Paging Unlimited

About the instructor

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