This course introduces the basic hardware structure of a modern programmable computer, including the basic laws underlying performance evaluation. We will learn, for example, how to design the control and data path hardware for a ARM-like processor, how to make machine instructions execute simultaneously through pipelining and simple superscalar execution, and how to design fast memory and storage systems. The principles presented in the lecture are reinforced in the laboratory through the design and simulation of a register transfer level (RTL) implementation of a MIPS-like pipelined processor in Verilog. In addition, we will develop a cycle-accurate simulator of this processor in C, and we will use this simulator to explore processor design options. (from ece.cmu.edu)